Conventionally, a known wiring substrate includes alternately layered wiring layers and insulating layers in which the wiring layers are connected to each other by way of a via hole penetrating the insulating layers. In this wiring substrate, a pad that is to be connected to a semiconductor chip or the like may be formed to project from a surface of an insulating layer. The pad may include a copper layer that is formed to project from the surface of an insulating layer and a surface plating layer that is formed to have a nickel layer and a gold layer sequentially layered on the upper and side surfaces of the copper layer. The amount in which the pad projects from the surface of the insulating layer including the surface plating layer may be approximately 15 μm to 50 μm (see, for example, Japanese Laid-Open Patent Publication No. 2010-251552).
However, in a case where the pad projects from the surface of the insulating layer, the surface plating layer may be damaged during a process of manufacturing a wiring substrate. In order to prevent such problem, a solder resist layer may be provided in the periphery of the pad. However, the solder resist layer requires to be substantially thick (e.g., approximately 20 μm to 60 μm) so that the upper surface of the solder resist layer is higher than the upper surface of the surface plating layer. This makes thickness reduction of the wiring substrate difficult.
Although thickness reduction of the wiring substrate can be achieved to some degree by reducing the thickness of the nickel layer, connection reliability (wettability) of the pad during wiring bonding or flip-chip bonding may be degraded. Further, by reducing the thickness of the nickel layer, the barrier effect of the nickel layer may become insufficient due to the thickness of the nickel layer being significantly reduced at the side surface of the copper layer. This may cause copper to spread to the solder formed on the pad.